1. Field of the Invention
The present invention relates to a technique of noise reduction in a power source of a semiconductor memory device.
2. Description of the Related Art
Typical examples of the semiconductor memory device include DRAM and SRAM. As is well known, the DRAM is more affordable in price and has a larger capacity than the SRAM, but requires the refreshing operation. The SRAM does not require any refreshing operation and is easily handled, but is more expensive and has a smaller capacity than the DRAM.
A virtual SRAM (called VSRAM or PSRAM) is known as a semiconductor memory device having the advantages of the DRAM and the SRAM. The virtual SRAM has a memory cell array of dynamic memory cells like the DRAM, and includes a refresh controller to perform the internal refreshing operation. An external device (for example, a CPU) connecting with the virtual SRAM can thus gain access to the virtual SRAM (for reading or writing data) without being specifically conscious of the refreshing operation.
In the DRAM, multiple power source terminals are generally provided for each of a positive power source and a negative power source as external power supply terminals for supplying power. This arrangement prevents potential noise in the power source due to a variation in electric current running through the power source. In the SRAM, on the other hand, only one pair of power source terminals are generally provided for the positive power source and the negative power source. The power source terminals of the virtual SRAM typically have the same construction as that of the SRAM. The less number of the power source terminals may cause the virtual SRAM to be rather vulnerable to noise in the power source.
The object of the present invention is thus to solve the drawback of the prior art semiconductor devices and to provide a technique of preventing potential noise in a power source of a semiconductor memory device, such as a virtual SRAM.
In order to attain at least part of the above and the other related objects, the present invention is directed to a semiconductor memory device, which includes: at least one memory cell block including dynamic memory cells arrayed in a matrix; a row address decoder and a column address decoder that select a memory cell in the memory cell block, which is specified by an address including a row address and a column address; an output buffer that outputs data corresponding to the selected memory cell specified by the address; a preset circuit that presets an output level of the output buffer; and a preset control module that controls an operation of the preset circuit. The preset control module actuates the preset circuit to preset the output level of the output buffer prior to output of the data corresponding to the selected memory cell from the output buffer, at every output of the data corresponding to the memory cell selected by the column address decoder.
Here the operation xe2x80x98preset the output levelxe2x80x99 means that the output level of the output buffer is set to a level (intermediate level) between a level representing data xe2x80x981xe2x80x99 and a level representing data xe2x80x980xe2x80x99, prior to output of data from the output buffer.
In this arrangement, the output level of the output buffer is set to the intermediate level, prior to output of data from the output buffer. The variation in output level in the course of data output is accordingly smaller than the variation from the level H to the level L of the variation from the level L to the level H. This arrangement thus effectively prevents potential noise in the power source, due to a variation in output.
In accordance with one preferable application, the preset control module actuates the preset circuit to preset the output level of the output buffer in response to every change of the column address in a consecutive output mode where the row address is fixed and the column address is varied.
In this application, the output level of the output buffer is preset in response to every change of the column address, in the consecutive output mode where the row address is fixed and the column address is varied.
In accordance with another preferable application, the semiconductor memory device further includes an output enable signal input terminal, which receives an output enable signal for defining output state from the output buffer. In the case where the output enable signal is in an output forbid state, the preset control module actuates the preset circuit to preset the output level of the output buffer after the output enable signal is set in an output enable state.
The output enable signal may be set in the output enable state after output of data from the memory cell specified by the address. In the case where the preset operation of the output buffer has already been concluded prior to the setting of the output enable signal in the output enable state to allow output of data from the selected memory cell by means of the output buffer, the output level at the time of the setting may be deviated from the output level at the time of conclusion of the preset operation. The above arrangement desirably prevents such a deviation of the preset output level.
It is preferable that the output level of the output buffer is preset by the preset circuit to a substantially intermediate level between a level representing data xe2x80x981xe2x80x99 and a level representing data xe2x80x980xe2x80x99.
In this application, the variation in output of the output buffer is substantially half the variation from the level H to the level L or the variation from the level L to the level H. This application thus minimizes the variation in output.
In one preferable embodiment, the semiconductor memory device has multiple memory cell blocks, and multiple row address decoders and column address decoders, which corresponding to the respective memory cell blocks. The address includes a block address for selecting one arbitrary memory cell block among the multiple memory cell blocks. The preset control module actuates the preset circuit to preset the output level of the output buffer prior to output of the data corresponding to the selected memory cell from the output buffer, at every output of the data corresponding to the memory cell selected by the column address decoder in one memory cell block specified by the block address.
In this embodiment, at every output of the data corresponding to the memory cell selected by the column address decoder in one memory cell block specified by the block address, the output level of the output buffer is preset prior to output of the data corresponding to the selected memory cell from the output buffer.
In accordance with still another preferable application, the semiconductor memory device is provided with a pair of power source terminals, one positive power source terminal and one negative power source terminal, as only power supply terminals for supplying power to the semiconductor memory device.
The semiconductor memory device with only one pair of power source terminals is relatively vulnerable to the power supply noise. The semiconductor memory device of the above application, however, effectively prevents the potential noise in the power source.
The technique of the present invention may be actualized by a diversity of applications; for example, a semiconductor memory device, a method of presetting an output buffer in the semiconductor memory device, a semiconductor memory system including the semiconductor memory device and a controller, a method of controlling the semiconductor memory device, and an electronic apparatus including the semiconductor memory device.